{fast, correct}
SystemVerilog, choose two.
The fast, complete SystemVerilog engine. Run your hardware designs dramatically faster without rewriting your testbenches or cutting corners on how simulation behaves. No compromises.
$ athena cpu.sv tb.sv
VS ICARUS VERILOG · picorv32
17×
30.9 s → 1.77 s
a full RISC-V core, same run
HOW ATHENA WORKS
Your design, compiled on the fly.
The fastest RTL simulators compile your design to optimized C++ and machine code. Athena goes further: like many programming languages, it JITs your design on the fly, keeping the performance of compiled code at a fraction of the startup time.
Athena uses LLVM to skip the C++ altogether, enabling better optimization and reducing compile time dramatically. Combined with build caching, warm runs start up in milliseconds.
Athena uses full event-driven semantics: stratified event scheduling,
accurate time modeling, four-state (0, 1, X, Z) logic.
No compromises.
BENCHMARKS
We measured it. Here’s the tape.
Time waiting for a simulator is time you're not iterating. Athena leaves Icarus in the dust, starts up faster than Verilator, and is competitive with many established simulators.
A complete RISC-V CPU executing real firmware — the closest thing to a representative, everyday workload. Athena finishes about 17× sooner than Icarus Verilog.
A large lookup table — the kind of decode logic real designs are full of. Athena turns it into a single direct jump instead of a long checklist, edging past even Verilator (a cycle-accurate simulator) by 3.3×.
A common hardware pattern for picking the first active signal. Athena maps it directly to a single CPU instruction rather than checking each option in turn — and again edges past Verilator.
Hundreds of concurrent timers, all ticking on their own schedule. Athena’s scheduling keeps this cheap and stays about 8× ahead of Icarus Verilog.
HOW IS IT SO FAST?
Designed from the ground up, performance first.
Athena’s speed comes from careful design, inspired by Verilator and the fastest software compilers and JITs — V8, Julia, and Clang.
01 · THE FOUNDATION
Built on LLVM
Athena generates code through LLVM — the same production compiler backend behind Clang, Swift, and Julia. Athena inherits the most sophisticated code generator and optimizer for free.
Running real machine code is fundamentally faster than interpreting a design step by step — which is why Athena routinely beats interpreted simulators like Icarus Verilog by more than 10×.
Athena models four state logic very efficiently, and opportunistically drops down to two-state logic where it doesn't matter — without sacrificing behavioral correctness.
Inspired by Verilator, Athena reorders and combines a simulation's work to cut scheduling overhead while producing identical results.
Athena caches the machine code it generates, so re-running an unchanged design — or one with only small edits — skips the build and starts up in milliseconds.
{FAST, CORRECT} — CHOOSE TWO
Speed never comes at the cost of correctness.
Athena was designed carefully to follow IEEE 1800-2023, and its behavior is rigorously tested against established simulators. It doesn't cover the entire language yet, but coverage is growing quickly and it's able to run many real cores.
- Correct four state (0, 1, x, z) logic modeling
- Fully event-driven, stratified queue scheduler
- Behavior verified against established simulators
- Strong LRM (IEEE 1800-2023) coverage
- UVM readyCOMING SOON
Try it on your own design.
Athena is open source — no license fees, no per-seat limits. Clone it, point it at your RTL, and turn the hours you lose waiting on simulation into more iterations per day.